Low threshold transistor logic, e.g., CMOS, is desirable because it facilitates reducing the footprint of circuits, requires a smaller power supply capability, etc. But low threshold voltage logic suffers substantial leakage current during a non-active mode that can, e.g., negate the benefit of the reduced power consumption during an active mode.
The Background Art addressed the leakage problem with a multi-threshold MOS (MTMOS) architecture, e.g., MTCMOS-type, that serially couples a sleep transistor and a low threshold logic circuit between a system-supply voltage (VDD) and a system-ground voltage (VSS). The sleep transistor has a high threshold voltage and so exhibits low leakage current in a sleep mode, but is slower to switch to the active mode than a comparable low-threshold transistor. As its name suggests, the sleep transistor reduces the non-active mode current of the low-threshold device because it serially connects the low-threshold logic to VSS. The sleep transistor imposes little in the way of a switching-speed penalty because it is always on during the active mode of the low-threshold logic.
High threshold voltages are typically achieved by applying a body bias voltage (Vbb) to the sleep transistor. The requisite Vbb generator circuitry increases the foot print of the overall device. Also, the high threshold of the sleep transistor requires a larger channel size to obtain comparable current capability, which also increases the overall footprint.
The Background Art addressed the footprint problem associated with the Vbb generator circuitry by using a dynamic threshold MOS (DTMOS) transistor as the sleep transistor. In a DTMOS transistor, the gate is connected to the well (or, in other words, the transistor body), which forward biases the source/body junction. This eliminates the need for a separate Vbb generator circuit. As the gate voltage (Vgg) is used to bias the body, the threshold voltage varies with (or, in other words, is dynamic in proportion to) changes in the gate voltage.
Sub-threshold voltage leakage of a DTMOS transistor is generally low. But a high gate voltage which is also applied as Vbb can, in effect, forward bias one of the gate junctions (analogous to forward-biasing a diode) in the transistor and cause a forward-biased-diode-type leakage current. This is generally depicted in the circuit diagram of Background Art FIG. 3.
In Background Art FIG. 3, a leakage current path 302 is depicted. There the source, gate and body of a transistor 308 are connected to voltage VDD, which raises a node 304 is raised to voltage VDD. This has the effect of raising Vgg and thus Vbb for an NMOS transistor 306 to be about VDD, which forward biases the gate-source junction in NMOS transistor 306 and causes leakage.
Such junction forward-biasing can be solved by limiting Vgg to about 0.6 volts, which in Background Art FIG. 3 necessarily limits VDD to about 0.6 volts.